The present invention relates to an extending method of an input/output channel of an information processing system, and more particularly to an extending method of an input/output channel in an information processing system in which a plurality of virtual machines operates on a physical machine.
As a common method for operating a plurality of operating systems (hereinafter referred to as OSs) on a single information processing system, a technique called a virtual machine or logical partition (hereinafter referred to as a VM or LPAR) has been known. In this technique, a control program called a virtual machine control program (hereinafter referred to as a hypervisor) is operated on a physical machine, a plurality of LPARs are generated under control of the hypervisor and independent OSs are operated on the respective LPARS. In order to operated the plurality of LPARs on the single physical information processing system (physical machine), the hypervisor is provided with a function to allow the respective LPARs to share hardware resources of the physical information processing system. A method for allowing the respective LPARs to share the hardware resources includes a method for allocating the hardware resources in time-division fashion under control of the hypervisor, a method fore logically dividing the hardware resources and exclusively allocating them to the respective LPARs, and a method for allocating by the mixture of the above two methods.
On the other hand, as a prior art method of an input/output method of the information processing system, an extended channel system (hereinafter referred to as an ECS) has been known. In the ECS, a plurality of sub-channels which one-to-one correspond to a plurality of input/output devices are provided, transfer paths of output commands and data due to input/output operations between the sub-channels and the input/output devices are determined through a channel path selection circuit and the transfer paths are determined without intervention of a program which starts the input/output operations. Each sub-channel holds input/output configuration information containing an input/output number of the corresponding input/output channel and a physical channel path number to which the input/output device is connected, and initial information of the input/output configuration information of the sub-channel is stored in a memory of a service processor (hereinafter referred to as a SVP). In an initialization process of the information processing system, the input/output configuration information in the memory of the SVP is loaded in a hardware system area (hereinafter referred to as HSA) to which a user program in a main storage cannot access and it is used to control the input/output operations.
When the input/output operation in a virtual machine system is conducted under control of the ECS, a plurality of sub-channels are generated for one input/output device, and the input/output device and the sub-channels are controlled to correspond one-to-one for each of the plurality of LPARs. In this case, each sub-channel corresponding to one input/output device has an LPAR identification ID corresponding to a virtual machine ID and one of the input/output configuration information.
A maximum number of input/output channels (number of CHPs) of the extended channel system is determined by a hardware architecture of the physical information processing system, that is, a designated data length of the CHP defined in the input/output configuration information. For example, when the designated data length of the CHP of the input/output configuration information is 8 bits, the maximum number of input/output channels is 256 channels.
Accordingly, when two systems of the LPARs which are the virtual machines in the prior art are constructed and the physical input/output processors are logically divided and they are allocated to an LPAR1 and an LPAR2, an upper limit of a total number of input/output channels (total number of CHPs) of the number of input/output channels is restricted by the maximum number of input/output channels determined by the hardware architecture having the number of input/output channels mounted as the physical input/output processors. For example, when the designated data length of the CHP in the input/output configuration information determined by the hardware architecture of the physical information processing system is 8 bits, the maximum total number of input/output channels which may be designated in the LPAR1 and the LPAR2 is 256 channels.
Accordingly, in the prior art method of logically dividing the physical input/output processors and the input/output channels (CHPs) and allocating them to the respective LPARs, it is not possible to conduct the input/output operations by using the number of CHPs which exceeds the maximum number of input/output channels determined by the hardware architecture.